1. Field of the Invention
This invention relates to memory devices, and more particularly to a memory device such as a dynamic random access memory (DRAM) that has dielectric compositions stable or resistant to H.sub.2 and other anneal treatments and is stable to a reducing atmosphere.
2. Description of Related Art
Since its introduction more than three decades ago, the dynamic random access memory has been successfully adopted as a device to store information in the form of charge [see L. H. Parker and A. F. Tasch, IEEE Devices and Circuit Magazine, January 1990, p. 17]. One of the more popular configurations for the memory cells in these devices involves a single capacitor in which charge is stored, and a single transistor that is used to isolate the capacitor. Over the years, as the number of memory cells has been increased from 4 kilobits (kb) in the original designs to Megabit (Mb) levels in the current designs, there has been a constant reduction in the available area per memory cell to maintain acceptable die sizes. This reduction in area has made it necessary to increase the charge density on the capacitor to maintain adequate signal margins. Some of the ways through which this increased charge storage density has been achieved is through improvements in process technology, reduction in dielectric thickness and innovative cell geometries. For cell densities up to 64 Mb, the preferred dielectric material and capacitor geometry has been a SiO.sub.2 -Si.sub.3 N.sub.4 sandwich layer. For future generation memories, DRAM memory units must have an increasingly high capacitance per unit area [C/A, with leakage currents on the order of 10.sup.-7 A. The following equation relates the capacitance per unit area to the appropriate material parameters: EQU [C/A]=[Er/d]
where Er is the relative dielectric constant, and d is the capacitor's dielectric film thickness. In the past, with SiO.sub.2 as the dielectric material, the capacitance per unit area was boosted in each successive generation by simply reducing its film thickness (d) or by using innovative geometries to increase the effective area of the capacitor on a given substrate. However, SiO.sub.2 is quickly approaching its capacitance per unit area limit, as further decreases in the thickness will eventually lead to an unacceptably high leakage current and increasing processing difficulties. Therefore, for higher density memories (e.g., 256 Mb and above) to be used with the same charge-storage concept, it becomes necessary to find alternate dielectric materials that can store a greater charge density. In other words, alternate dielectric materials with higher dielectric constants (compared to SiO.sub.2 Si.sub.3 N.sub.4) need to be used. In addition, these materials must also be compatible with VLSI (very large scale integration, used herein to encompass U(ltra) LSI and the like) processing.
One of the primary candidates for capacitor dielectrics in future generation DRAMs is barium strontium titanate (Ba.sub.x Sr.sub.1-x TiO.sub.3, 0&lt;x&lt;1) (BST). This compound is essentially a solid solution of BaTiO.sub.3 and SrTiO.sub.3 and crystallizes in the perovskite type structure with a chemical formula ABO.sub.3. The dielectric constant exhibited by these materials can vary between 200-600 at room temperature and zero bias depending on the composition [Ba/Sr ratio], frequency of measurement and thickness of the material. The thin film processibility of these materials has been demonstrated in our own laboratory and in several other recent works wherein high quality stoichiometric compositions of these materials have been produced by metalorganic decomposition, metalorganic chemical vapor deposition, sputtering, laser ablation, etc. [see K. V. Belanov, E. A. Goloborod'ko, O. E. Zavadovski, Yu. A. Kontsevoi, V. M. Mukhorotv and Yu. S. Tikhodeev, Sov. Phys. Tech. Phys., 29, 1037, 1984; D. Roy and S. B. Krupanidhi, Appl. Phys. Lett., 62, 1056, 1993; W. A. Feil, B. W. Wessels, L. M. Tonge and T. J. Marks, J. Appl. Phys., 67,3858, 1990; B. W. Wessels, L. A. Willis, H. A. Lu, S. R. Gilbert, D. A. Neumayer and T. J. Marks, in CVDXII, edited by K. Jensen, Electrochemical Society, N.J., 1993]. The qualification of these capacitors is typically done by measuring their current-voltage (leakage current) characteristics and their dielectric behavior (dielectric constant and dielectric loss) in the desired frequency and temperature ranges.
However, one of the primary reliability problems that may preclude the use of these materials as capacitor dielectrics for DRAM applications is their poor resistance to reducing environments (e.g., H.sub.2 anneal treatments). Because of their high melting points and their strong tendency towards reduction in low oxygen partial pressures, compositions that are based on alkaline-earth titanates require both high temperatures and oxidative environments for their processing. These titanates, when heat treated in reducing atmosphere, become highly conductive due to the conversion of Ti.sup.4+ ions into Ti.sup.3+ ions accompanying the formation of oxygen vacancies. In terms of VLSI fabrication this is a major disadvantage because of the several post processing steps (after the capacitor fabrication) involving the use of reducing atmospheres. Some of these steps include (a) the deposition of SiO.sub.2 or Si.sub.3 N.sub.4, for passivation or encapsulation using SiH.sub.4 precursors during which H.sub.2 is released as the product gas and (b) forming gas (90% N.sub.2 +10% H.sub.2) treatments after the aluminum metallization depositions for oxide removal. For BST based DRAMs to be a viable memory product, it is necessary to identify a processing scheme that is capable of inhibiting the reduction of these alkaline-earth titanates.
In this disclosure we describe a thin film device and the associated processing scheme, for use as a dielectric capacitor in a DRAM cell. This device meets all the standard device quality requirements (I/V characteristics, dielectric constant, dielectric loss, etc.) and is also capable of withstanding drastically reducing atmospheres.